1. Field of the Invention
This invention relates to a high-speed signal multiplexing circuit for multiplexing high-speed signals for use in an integrated circuit for a high-speed communication system or a measuring device for measuring high-speed signals.
2. Description of the Related Art
FIG. 4 shows a conventional high-speed signal multiplexing circuit.
A shift register section 31 includes D-type flip-flop circuits (hereinafter referred to as D flip-flop circuit) 32.sub.0, 32.sub.1, 32.sub.2, and 32.sub.3, and selector circuits 34.sub.0, 34.sub.1, 34.sub.2, and 34.sub.3 respectively connected to input terminals D of the D flip-flop circuits 32.sub.0, 32.sub.1, 32.sub.2 and 32.sub.3. Each of the selector circuits 34.sub.0, 34.sub.1, 34.sub.2 and 34.sub.3 comprises AND circuits 33.sub.1 and 33.sub.2 and an OR circuit 33.sub.3. The selector circuits 34.sub.1, 34.sub.2 and 34.sub.3 select either data D.sub.1, D.sub.2 and D.sub.3 respectively supplied to input terminals I.sub.1, I.sub.2 and I.sub.3 or data supplied from output terminals Q of the flip-flop circuits 32.sub.0, 32.sub.1 and 32.sub.2 in response to a load signal LS supplied from a load signal generating section 35 (to be described later). The selector circuit 34.sub.0 selects either data D.sub.s supplied to an input terminal I.sub.s or data D.sub.0 supplied to an input terminal I.sub.0 in response to a load signal LS.
A clock signal CK is inverted by an inverter IV, and then supplied to clock signal input terminals CK.sub.0 to CK.sub.3 of the D flip-flop circuits 32.sub.0 to 32.sub.3. Data latched by the D flip-flop circuits 32.sub.0 to 32.sub.3 are successively shifted in response to clock signals CK, and output through output terminal D.sub.OUT. Thus, data latched in the shift register section 31 is output through the output terminal D.sub.OUT by four shifting operations.
The load signal generating section 35 generates a load signal LS for causing data D.sub.S and D.sub.0 to D.sub.3 supplied to the input terminals I.sub.s and I.sub.0 to I.sub.3 to be latched by the D flip-flop circuits 32.sub.0 to 32.sub.3 by every four shift operations. The load signal LS is obtained by 1/4 frequency-dividing the clock signal CK, as is shown in FIG. 5.
The load signal generating section 35 includes D flip-flop circuits 36 and 37, a NOR circuit 38 for generating a load signal from outputs of the flip-flop circuits 36 and 37, and a selector circuit 40 connected to an input terminal D of the D flip-flop 36. The selector circuit 40 comprises AND circuits 39.sub.1 and 39.sub.2 and a OR circuit 39.sub.3. An output terminal Q.sub.1 of the flip-flop circuit 36 is connected to an output terminal SO.
The selector circuit 40 switches the control system of the selector circuits 34.sub.0 to 34.sub.3 between an external synchronous mode and an internal synchronous mode. In other words, the selector circuit 40 selects either a signal output from an output terminal Q of the D flip-flop circuit 37 or a 1/4 frequency-divided clock signal SI in response to an inhibit signal INH. The load signal generating section 35 generates a load signal LS in response to a signal SI selected by the selector circuit 40 in the case of the external synchronous mode, and in response to an output signal of the D flip-flop circuit 37 selected by the selector 40 in the case of the internal synchronous mode.
In the above-described conventional high-speed signal multiplexing circuit, the selector circuits 34.sub.0 to 34.sub.3 is controlled by a load signal LS generated asynchronously with input data. To generate a load signal LS in the external synchronous mode, the high-speed signal multiplexing circuit must control the phases of a clock signal CK, a signal SI having a frequency of four times that of the clock signal, and data D.sub.s, D.sub.0 to D.sub.3. Hence, the circuit design is complicated and it is difficult to increase the margin of the operation of the circuit.
Especially in a circuit operated by a signal having a high frequency of a GHz band, since signal transmission is performed by a distributed constant circuit and the resolution of the phase control is of pico-second order, it is quite difficult to control the phase of a signal externally.
On the other hand, to generate a load signal LS in the internal synchronous mode, it is only necessary to control the phases of the clock signal and data D.sub.s, D.sub.0 to D.sub.3, since a load signal LS is generated from a clock signal to control the selector circuits 34.sub.0 to 34.sub.3. However, in this case, to increase the operation margin of the entire circuit, the phases of the data, the load signal, and the clock signal for operating the shift register section 31 must be controlled. Therefore, the circuit design is complicated.
Thus, also in the case of controlling a phase in the internal synchronous mode, an operation of a wide margin in a high-frequency band in a GHz band cannot be achieved unless the circuit is designed with defining a signal which is to be phase-controlled.